entity test is
    port(
        a, b : in bit;
        s: in bit;
        y: out bit
        );
end entity test;

entity test2 is
    port(
        a: in bit;
        b: out bit;
        c: inout bit;
        d: buffer bit;
    );
end entity test2;

entity test3 is 
    port(
        a: in bit;          -- 0/1
        b: in bit_vector;   -- 位矢量
        c: in std_logic;    -- 逻辑类型，0/1/H/L/Z/X/W/U/- 9种，描述单个信号引脚
    );
end entity test3;

entity test4 is
    generic(w: integer: =16);   --常数属性
    port(abus: out bit_vector (w-1 downto 0));
end entity test4;

--architecture
architecture one of test is
    begin
    y <= a when s = '0' 
        else b;
end architecture one;


-- 【数据对象】 --

-- 常数
constant one: bit_vector := "0101";
constant two: integer := 8;

-- signal
signal count: bit_vector (7 downto 0); --初始化赋值只在仿真由于综合时被忽略
count <= count + 1;
count <= x"aa";
count(7) <= '1';
count(7 downto 4) <= "1010";

-- variable
variable x,y : integer range 15 downto 0;
variable a,b : std_logic_vector(7 downto 0);
b := "010101";
a := b;

-- 【数据类型】 --

-- 1.标准数据类型 --
integer real bit bit_vector boolean character time 
severity natural positive string

-- 2.用户定义的数据类型 --
-- integer
type A is integer range -63 to 63;
variable a: A := 10;
-- enum
type Status is (idea, decision, read, write);
type Week is (mon, tue, wed, thu, fri, sat, sun);
variable a_status: Status;
variable a_week: Week := mon;
-- array
type Byte is array (7 downto 0) of bit;
type Workd is array (63 downto 0) of Byte;  -- 二维数组
type bit_vector is array (integer range <>) of bit;
-- 子类型(对某个类型添加约束)
subtype my_vector is bit_vector (0 to 15);
-- 记录类型 record (不同类型组织在一起构成新类型)
type Month is (Jan, Fab, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec);
type Date is record
    day: integer range 1 to 31;
    month: Month;
    year: integer range 0 to 3000;
end record;
variable today: Date;
today := (14, Aug, 2024);

-- 3.IEEE标准数据类型
-- std_logic
U, X, 0, 1, Z, W, L, H, -
-- std_logic_vector
-- unsigned signed
signal a: unsigned (3 downto 0);
variable b: signed (3 downto 0);

-- 4. 类型转换 --
to_integer();
to_unsigned();
unsigned();
bit_vector();
to_stdlogicvector();
to_bitvector();
to_stdlogic();
to_bit();
conv_std_logic_vector(a*n);
conv_integer();
conv_integer();

signal data: std_logic_vector (2 downto 0);
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
signed num: integer range 0 to 7;
num <= conv_integer(data);  -- data位宽为3位，num最大值7


-- 【属性】 --

-- 1. 值类型
type count is integer range 0 to 127;
count'left = 0, count'right = 127, count'low = 0, count'high = 127,
count'length = 128, count'range = 0 to 127;

-- 2. 函数类属性 
'event, 'active, 'last_event, 'last_value, 'last_active,
if clk'event and clk = '1' then -- 判断clk信号是否发生变化且变化位1，即clk的上升沿
if clk'event and clk = '0' then -- 判断clk信号是否发送变化且变化位0，即clk的下降沿




